Electronic circuits, such as integrated circuits, are used in a variety of electronic systems, from automobiles to microwaves to personal computers. Designing and fabricating circuits typically involves many steps, known as a “design flow.” The particular steps of a design flow often are dependent upon the type of circuit being designed, its complexity, the design team and the circuit fabricator or foundry that will manufacture the circuit. Software and hardware “tools” are typically used at various stages of the design flow to aid in developing the design and in ensuring that the design is free from errors. The process of using hardware and software tools to aid in the design flow is often referred to as electronic design automation (EDA).
Several steps are common to most design flows. Typically, the specification for a new circuit is first described at a very abstract level. More particularly, relationships between a set of inputs and a set of outputs are described using a set of computations. This is referred to as an “algorithmic level” design or “algorithmic specification” and is often described using conventional computer programming languages, such as, for example, C++. The algorithmic specification is then subsequently transformed, often referred to as “synthesized,” into a design having a lower level of abstraction.
Typically, designers synthesize the algorithmic specification into a Register Transfer Level (RTL) description of the circuit. With this type of description, the circuit is defined in terms of both the exchange of signals between hardware registers and the logical operations that are performed on those signals. Subsequently, the design is further synthesized into lower and lower levels of abstraction. For example, the register transfer level design may be synthesized into a gate-level design. At each abstraction level, the design is typically described by a hardware description language (HDL), such as, for example, the Very high speed integrated circuit Hardware Design Language (VHDL).
The gate-level design, which is typically in the form of a schematic or netlist, describes the specific electronic devices (such as transistors, resistors, and capacitors) that will be used in the circuit, along with their interconnections. This gate-level design generally corresponds to the level of representation displayed in conventional circuit diagrams. The gate-level design can then be synthesized into a design for a mask, which, as those of ordinary skill in the art will appreciate, is used to manufacture the design.
During various stages of the design flow, the behavior of the design is checked to ensure that it corresponds with the intended or expected behavior. This is often referred to as “verification.” If errors in the design are found during verification, they can be corrected at this stage of the design process. Additionally, the design may be modified to account for known effects that may cause errors during the operation of the design. One known effect is referred to as a single event upset (SEU). A SEU is an unwanted change of the data in a state element, such as, for example, a register. As those of ordinary skill in the art will appreciate, an SEU is random in nature, and will often cause unwanted behavior in the device design when manifest.
Various techniques have been proposed to deal with the effects of an SEU. For example, triple mode redundancy (TMR) replicates a portion of the design twice, resulting in three separate identical design portions. Subsequently, these design portions can be checked against each other to ensure consistency. Although TMR is generally effective, it requires replicating the design, which adds to the size and costs associated with the design. Another technique to mitigate SEU effects is to record the same signal at three different times. More specifically, the same signal is sampled at three different times and then recorded into a state element. These state elements are later synchronized to ensure consistency between the signal samplings. Although this solution can be implemented without replicating the design portions, it still degrades the operating speed of the design.